With the continuous progress in electric industry, more and more electrical device are developed and employed in daily life to improve convenience and living qualities. Computers, communications, and consumer products are identified to be most impressive applications of the twentieth century. In various applications, memory devices are inevitably utilized as vital elements in providing essential information and providing storage space for data exchange. In recent years, one of the non-volatile memories, flash memories, are employed in more and more applications.
With the non-volatile characteristics, the flash memories can be programmed with numerous times and maintaining the programmed state without the need of a continuously supplied power. The flash memories has been widely applied in various memorization usage. With the continuous narrowing or scaling down of the semiconductor processes in manufacturing flash memories, the number of flash cells per unit chip area can be raised and the operating characteristics can be improved.
Referring to FIG. 1, a schematic diagram of four neighboring flash cells 10, 12, 14 and 16 is illustrated. It is a well known design in a flash array for cells to share a common source region or common source line in a group. The flash cells 10, 12, 14 and 16 share a common line SL, as indicated in the figure. The flash cells 10 and 12 have a common word line WL0 and the flash cells 14 and 16 have another common word line WL1. The drain junctions of the flash cells 10 and 14 are connected to a common bit line BL0 and the drain junctions of the flash cells 12 and 16 are connected to another common bit line BL1. During the programming process of a flash memory array with staked gate design, a cell to be programmed, for example the cell 10, is selected with the corresponding bit line BL0 and the corresponding word line WL0. A programming voltage is applied to the common source line SL and a selecting voltage is applied to the word line WL0. In general, the selecting voltage is about the value of the threshold voltage Vt of the transistor. The bit line BL0 of the selected cell 10 is about VSS and the unselected bit line BL1 is at about VDD or about VDD-Vt, wherein VDD and VSS respectively represent a high state and a low state of the operating voltages of the flash memory cells.
With the selecting process and an appropriate voltage, the selected cell 10 can be programmed with the designed state. However, the unselected cell 12, which is supposed to maintain it's original state without the influence of the programming process, is found to be easily disturbed with the configuration. During the programming of the cell 10, the source of the cell 12 has a high programming voltage, for example a voltage of 12 volts. The drain of the cell 12 is set at about VDD or about VDD-Vt. The source to drain voltage is about 12-VDD or (12 -VDD+Vt) for the unselected cell 12. The voltage difference as high as 8 to 9 volts is large enough to cause the punch-through disturb to the cell. With the continuous narrowing down of the cell size and the operating voltage of the flash cells, the flash cells being operated at low VDD is found to seriously suffer the harm of programming or writing disturbance.